High speed ECL output circuit having reduced power consumption

ABSTRACT

The output circuit according to the present invention includes a bipolar transistor (Q 1 ), a resistance (R 1 ) and a constant current source. The transistor (Q 1 ) has its collector connected to a power supply node (V CC ), its emitter connected to an output node (Do), and its base connected to the other end of the resistance (R 1 ). The resistance (R 1 ) has one end connected to the power supply node (V CC ). The constant current source is connected between a power supply node (V EE ) and the base of the transistor (Q 1 ) and is turned on/off in response to an input signal (IN) to generate a current (I 1 ) for bringing output into a low level only in the on state. The constant current source does not generate the current (I 1 ) at the time of output of a high level, and causes the current (I 1 ) to flow through the resistance (R 1 ) only at the time of output of a low level. As a result, power consumption can be reduced.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to output circuits of integratedcircuit devices, and more particularly, to an ECL output circuit.

2. Description of the Background Art

With recent progress of a semiconductor technology, a higher speed andhigher integration density are required. In order to satisfy suchrequirements, an emitter coupled logic (hereinafter referred to as an"ECL") circuit is used. An ECL output circuit is used only for a loadespecially requiring a high speed, while a complementary metal oxidesemiconductor (hereinafter referred to as a "CMOS") circuit is used fora circuit which does not require a high speed.

FIG. 12 is a schematic block diagram of a bipolar-CMOS integratedcircuit device made in combination of a CMOS logic array circuit and anECL logic array circuit.

Referring to FIG. 12, an integrated circuit device 200 includes an inputcircuit 10, an input circuit 20, an internal processing circuit 30, anoutput circuit 40, and an output circuit 50. Input circuit 10 receives asignal converted to a logic level of the CMOS circuit to provide a j-bitsignal to internal processing circuit 30. Input circuit 20 receives asignal converted to a logic level of the ECL circuit to provide a k-bitsignal to internal processing circuit 30. Internal processing circuit 30processes j-bit and k-bit signals from input circuits 10 and 20,respectively, to provide m-bit and n-bit signals to output circuits 40and 50, respectively. Output circuit 40 converts the m-bit signal to alogic level corresponding to the CMOS circuit to provide the same.Output circuit 50 converts the n-bit signal to a logic level of the ECLcircuit to provide the same. The signal converted to the logic level ofthe CMOS circuit is applied to a circuit providing a signal of a CMOSlogic level, for example, a main memory operating at a relatively lowspeed. The signal of the ECL logic level is applied to a circuitoperating at a high speed, for example, a cache memory.

Such an ECL output circuit operating at a high speed is described inFIG. 9 of "A 10k-GATE 950-MHz CML Demonstrator Circuit Made with a 1 μmTrench-Isolated Bipolar Silicon Technology", pp. 552-557, in IEEEJournal of Solid-State Circuits, Vol. 24, No. 3, June 1989, and in FIG.2 of "A 50-ps 7k-Gate Masterslice Using Mixed Cells Consisting of an NTLGate and an LCML Macrocell", pp. 202-207, in IEEE Journal of Solid-StateCircuits, Vol. SC-22, NO. 2, April 1987.

FIG. 13 is a schematic diagram of a conventional ECL output circuitsimilar to the ECL circuit described in the aforementioned documents.

An ECL output circuit 50 shown in FIG. 13 includes a constant currentsource 51, a differential amplifier 52, an output bipolar transistor Q₁,a power supply node V_(CC) having a first power supply voltage V_(CC)supplied thereto, a power supply node V_(EE) having a second powersupply voltage V_(EE) supplied thereto, an output node Do, and inputnodes IN, /IN. The output node Do is connected to a terminal voltageV_(TT) through a terminal resistance R_(T). Generally, an ECL outputcircuit, the power supply node V_(CC), the power supply node V_(EE), andthe terminal voltage V_(TT) are 0 V, -5.2 V, and -2 V, respectively. Thebipolar transistor Q₁ has its collector connected to the power supplynode V_(CC), its emitter connected to the output node Do, and its baseconnected to differential amplifier 52. Differential amplifier 52includes transistors Q₃ and Q₄ and resistances R₁ and R₁₀. Thetransistor Q₃ has its collector connected to the power supply nodeV_(CC) through the resistance R₁₀, its emitter connected to constantcurrent source 51, and its base connected to the input node IN. Thetransistor Q₄ has its collector connected to the power supply nodeV_(CC) through the resistance R₁, its emitter connected to constantcurrent source 51, and its base connected to the input node /IN.Operations of the ECL output circuit shown in FIG. 13 will now bedescribed. Input signals IN, /IN are applied to bases of transistors Q₃and Q₄, respectively, and an output signal is taken out from the emitterof the transistor Q₁.

The case where a signal of a high level is applied to the input node INand a signal of a low level is applied to the input node /IN will now beconsidered. Since the transistor Q₃ is turned on in response to theinput signal IN and the transistor Q₄ is turned off in response to theinput signal /IN, the base of the transistor Q₁ is connected to thepower supply node V_(CC) through the resistance R₁. A path from thepower supply node V_(CC) to the resistance R₁ to the base-emitter of thetransistor Q₁ to the output node D₀ is thus configured. A current I_(B)flows to the base of the transistor Q₁ through the resistance R₁ overthe path, whereby an output voltage V_(OH) of a high level can beobtained at the emitter of the transistor Q₁. The output voltage V_(OH)is expressed by an equation (1) when V_(be) represents the base-emittervoltage in the on state of the transistor Q₁ :

    V.sub.OH =V.sub.CC -R.sub.1 ×I.sub.B -V.sub.be       ( 1)

where V_(be) is generally 0.7 to 0.8 V.

On the other hand, when a signal of a low level is applied to the inputnode IN, and a signal of a high level is applied to the input node /IN,the transistor Q₃ is turned off, and the transistor Q₄ is turned on,whereby constant current source 51 is connected to the base of thetransistor Q₁. A current I₁ and the base current I_(B) generated byconstant current source 51 flow to the resistance R₁. The output voltageV_(OL) is given by an equation (2).

    V.sub.OL =V.sub.CC -R.sub.1 (I.sub.1 +I.sub.B)-V.sub.be    ( 2)

The output voltage V_(OL) is lower than the output V_(OH) of a highlevel by R₁ ×I₁. In the case of the ECL output circuit, R₁ ×I₁ isapproximately 1 V.

As described above, the output signal is changed to V_(OL) and V_(OH)according to the level of the input signal.

In the conventional ECL output circuit, differential amplifier 52 isused for applying a suitable potential to the output transistor Q₁.Therefore, even when the output V_(OH) of a high level is provided, asteady current flows through the transistor Q₃, causing a problem thatelectric power is continuously consumed. Since a recent semiconductordevice has an increased number of output circuits with increase of theamount of information, a large amount of power is consumed as a whole.Therefore, it is necessary to reduce power consumption.

When a current amplification factor hfe of the output transistor Q₁ isnot high, it is necessary to obtain a desired output voltage byincreasing the base current I_(B). However, when the base current I_(B)is increased, a voltage drop R₁ ×I_(B) in providing the high levelV_(OH) is increased. Therefore, it is not possible to obtain V_(OH) of asufficiently high level unless the resistance R₁ is decreased. However,when the resistance R₁ is decreased, the voltage drop R₁ (I_(B) +I₁) inproviding the low level V_(OL) is decreased. Therefore, in order toobtain the low level V_(OL) of a sufficiently low level, the current I₁must be increased. Therefore when the current amplification factor hfeis not high, there is a probability that power consumption in providingthe low level V_(OL) is increased.

In order to eliminate the problem, the current amplification factor hfeof the output transistor Q₁ can be increased. However, in order toincrease the current amplification factor hfe of the transistor Q₁, itis necessary to control the concentration of impurity precisely,resulting in high costs.

SUMMARY OF THE INVENTION

One object of the present invention is to reduce power consumption atthe time of output of a high level in an output circuit operating at ahigh speed.

Another object of the present invention is to reduce power consumptionat the time of output of a low level in an output circuit operating at ahigh speed.

Still another object of the present invention is to reduce powerconsumption at the time of output of high and low levels in an outputcircuit operating at a high speed.

Briefly, the output circuit according to the present invention includesa first power supply node having a first supply voltage suppliedthereto, a second power supply node having a second power supply voltagesupplied thereto, an output node for providing an output signal of apredetermined logic level, a transistor, a resistor, and a currentgenerator. The transistor has its collector electrode connected to thefirst power supply node, and its emitter electrode connected to theoutput node. The resistor has its one end connected to the first powersupply node, and the other end connected to the base electrode of thetransistor. The current generator is connected between the baseelectrode of the transistor and the second power supply node to beturned on/off in response to an input signal, generating a current forbringing an output signal into a low level only in the on state.

In operation, the current generator is turned on/off in response to theinput signal, and generates a current for bringing the output signalinto a low level only in the on state. Therefore, when the currentgenerator is in the off state, only the resistor is connected to thebase of the transistor, and the emitter of the transistor provides anoutput of a high level. On the other hand, when the current generator isin the on state, a current generated by the current generator flows tothe resistor, generating a voltage drop to bring the output signal intoa low level. When the output signal is brought into a high level, thecurrent generator does not generate a current, whereby power consumptioncan be reduced.

In another aspect, the output circuit according to the present inventionincludes a first power supply node, a second power supply node, anoutput node, a transistor and a resistor. The output circuit furtherincludes first to third switching circuits, and a constant currentgenerator. The first switching circuit has a predetermined on-resistancevalue, is connected to the resistor in parallel, and is turned on/off inresponse to an input signal. The constant current generator is connectedto the second power supply node to generate a constant currentcontinuously. The second switching circuit is connected between theconstant current generator and the base electrode of the transistor tobe turned on/off in a manner complementary to the first switchingcircuit in response to an input signal, applying a constant currentgenerated by the constant current generator to the base electrode of thetransistor in the on state. The third switching circuit is connectedbetween the constant current generator and the first power supply nodeto be turned on/off as well as the first switching circuit in responseto an input signal.

In operation, because of provision of the first switching circuit whichhas a predetermined on-resistance value, is connected to the resistor inparallel, and is turned on/off in response to the input signal, theresistor and the on-resistance are connected in parallel to decrease theresistance value of the parallel circuit, causing the voltage drop to besmall when the first switching circuit is in the on state, that is, whenthe output signal is brought into a high level. As a result, it ispossible to make the high level sufficiently high. Conversely, when thefirst switching circuit is in the off state, that is, when the outputsignal is brought into a low level, the resistance value of the parallelcircuit becomes high, whereby it is possible to make high the voltagedrop at the base of the transistor. Even though the current for bringingthe output signal into a low level is not increased, it is possible tomake the low level of the output signal sufficiently low. As a result,it is possible to reduce power consumption at the time of output of alow level.

In still another aspect, the output circuit according to the presentinvention includes a first power supply node, a second power supplynode, an output node, a resistor, a switching circuit, and a currentgenerator. The switching circuit has a predetermined on-resistancevalue, is connected to the resistor in parallel, and is turned on/off inresponse to an input signal. The current generator is connected betweenthe base electrode of the transistor and the second power supply node tobe turned on/off in a manner complementary to the switching circuit inresponse to the input signal, generating a current for bringing theoutput signal into a low level only in the on state.

In operation, it is possible to render a high level and a low level ofthe output signal sufficiently high and low, respectively, by decreasingthe resistance value by parallel connection of the resistor and theon-resistance at the time of output of a high level and by increasingthe resistance value at the time of output of a low level to be higherthan that at the time of the output of a high level, even if the currentfor bringing the output signal into the low level is not increased.Furthermore, since the current generator generates a current forbringing output into a low level only in the on state, it is possible toalso reduce power consumption at the time of output of a high level.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an output circuit showing oneembodiment of the present invention.

FIG. 2 is a schematic diagram of an equivalent circuit of FIG. 1 whenthe input signal IN is at a high level.

FIG. 3 is a schematic diagram of an equivalent circuit of FIG. 1 whenthe input signal IN is at a low level.

FIG. 4 is a schematic diagram of an output circuit showing a secondembodiment of the present invention.

FIG. 5 is a schematic diagram of a circuit showing one example of acontrol voltage generating circuit 2 shown in FIG. 4.

FIGS. 6 to 11 are schematic diagrams of circuits showing third to eighthembodiments of the present invention, respectively.

FIG. 12 is a schematic block diagram of a bipolar-CMOS integratedcircuit made in combination of a CMOS logic array circuit and an ECLlogic circuit.

FIG. 13 is a schematic diagram of a conventional ECL output circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a schematic diagram of a circuit showing one embodiment of theoutput circuit according to the present invention. An output circuit 60shown in FIG. 1 is different from an output circuit 200 shown in FIG. 13in that a resistance R₁ is provided in place of differential amplifier52, and that a constant current source 1 is provided which applies aconstant current I₁ only to a connection node N1 of the base of thetransistor Q₁ and the resistance R₁. Since FIG. 1 is similar to FIG. 13as for the other circuits, description will not be repeated by labelingthe same reference numerals.

The resistance R₁ has one end connected to the first power supply sourceV_(CC), and the other end connected to the node N1. The node N1 isconnected in common to the base of the transistor Q₁ and constantcurrent source 1. Constant current source 1 generates the constantcurrent I₁ when the input signal IN is at a low level, and is broughtinto the off state when the input signal IN is at a high level.

FIG. 2 is a schematic diagram of an equivalent circuit of FIG. 1 whenthe input signal IN is at a high level, while FIG. 3 is a schematicdiagram of an equivalent circuit of FIG. 1 when the input signal IN isat a low level.

Referring to FIGS. 1 to 3, operations of the output circuit shown inFIG. 1 will be described.

When the input signal IN is at a high level, constant current source 1is in the off state, causing the constant current I₁ not to flowanywhere. As a result, an ECL circuit 60 configures an equivalentcircuit as shown in FIG. 2. The current I_(b) is supplied to the base ofthe transistor Q₁ through the resistance R₁. The potential of theemitter of the transistor Q₁ is given by the following equation (3).

    V.sub.OH =V.sub.CC -R.sub.1 ×I.sub.b -V.sub.be       (3)

On the other hand, when the input signal IN is at a low level, theconstant current source 1 is in the on state, whereby ECL circuit 60configures an equivalent circuit shown in FIG. 3. The base of thetransistor Q₁ is provided with the current I_(b) through the resistanceR₁ as well as with the current I₁ from constant current source 1. As aresult, the potential of the emitter of the transistor Q₁ is given bythe following equation (4).

    V.sub.OL =V.sub.CC -R.sub.1 (I.sub.1 -I.sub.b)-V.sub.be    (4)

Only when the input signal IN is at a low level, the current I₁ flows tothe base of the transistor Q₁, and when the input signal IN is at a highlevel, the current I₁ does not flow anywhere, whereby it is possible toreduce power consumption in applying an output signal of a high level tothe data output node Do. When the ECL level is provided, R₁ ×I₁ can beset to approximately 1 V similarly to a conventional example.

FIG. 4 is a schematic diagram of a circuit showing another embodiment ofthe present invention. An output circuit 70 shown in FIG. 4 includes aconstant current source having a switching function as a current sourceof FIG. 1. Constant current source 1 includes a bipolar transistor Q₂, aresistance R₂, a control signal generating circuit 2, an NMOS transistorM₁, and an inverter 3. The transistor Q₂ has its collector connected tothe node N1, its emitter connected to one end of the resistance R₂, andits base connected to control signal generating circuit 2 through theNMOS transistor M₁. The resistance R₂ has its other end connected to thesecond power supply node V_(EE). The NMOS transistor M₁ has its gateelectrode connected to the output of inverter 3. Inverter 3 has itsinput connected to receive the input signal IN. Control signalgenerating circuit 2 generates a control voltage V_(CS). The controlvoltage V_(CS) is made constant in order to make the transistor Q₂ serveas a constant current source. For operation at the ECL level, V_(CS) isset to approximately -3.9 V.

FIG. 5 is a schematic diagram of a circuit showing one example ofcontrol voltage generating circuit 2 shown in FIG. 4. Referring to FIG.5, control voltage generating circuit 2 includes transistors Q₁₀ to Q₇₀,resistances R₁₀ to R₆₀, a first power supply node V_(CC), a second powersupply node V_(EE), and a control voltage output node V_(CS).

How to make constant the voltage of the control voltage output nodeV_(CS) will now be described.

The diode-connected transistor Q₁₀ generates a constant voltage in theon state. The difference ΔV_(be) between the constant voltage and thebase-emitter voltage of the transistor Q₃₀ is supplied to the resistanceR₅₀. As a result, the current flowing to the resistance R₅₀ becomesΔV_(be) /R₅₀. Since the emitter current is much larger than the basecurrent, by ignoring the base current of the transistor Q₄₀, thepotential V (N₁₀) of the node N₁₀ is given by an equation (5):

    V(N.sub.10)=V.sub.be (Q.sub.40)+R.sub.40 ·ΔV.sub.be /R.sub.50 +V.sub.be (Q.sub.20)                            (5)

where V_(be) (Q₄₀), V_(be) (Q₂₀) are base-emitter voltages of thetransistors Q₄₀, Q₂₀, respectively.

By designing the current density of the transistors Q₂₀ and Q₇₀ to bethe same, it is possible to have V_(be), (Q₂₀)=V_(be), (Q₇₀), wherebythe output voltage of the control voltage output node V_(CS) is given byan equation (6). ##EQU1##

As described above, by combining V_(be) (Q₄₀) having negativetemperature characteristics and ΔV_(be) ·R₄₀ /R₅₀ having positivetemperature characteristics, temperature compensation of the controlvoltage V_(CS) is made, whereby the control voltage V_(CS) is madeconstant. It should be noted that ΔV_(be) ·R₄₀ /R₅₀ is made by adjustingthe resistances R₅₀ and R₁₀.

Operations of the output circuit shown in FIG. 4 will now be described.When the input signal IN is at a high level, the NMOS transistor M₁ isturned off. The potential of the base of the transistor Q₂ is reducedbecause of its own base current, whereby the transistor Q₂ is broughtinto the off state. On the other hand, when the input signal is at a lowlevel, the NMOS transistor M₁ is in the on state, whereby the controlvoltage V_(CS) is supplied to the base of the transistor Q₂. Therefore,the difference between the control voltage V_(CS) and the base-emittervoltage V_(be) of the transistor Q₂ is applied to the resistance R₂,whereby a constant current of (V_(CS) -V_(be))/R₂ =I₁ flows to theresistance R₂.

As described above, constant current source 1 having a switchingfunction generates a constant current only at the time of output of alow level. Therefore, it is possible to cut the bias current at the timeof output of a high level, thereby making it possible to reduce powerconsumption.

FIG. 6 is a schematic diagram of a circuit showing still anotherembodiment of the present invention. An output circuit 80 shown in FIG.6 is different from output circuit 70 shown in FIG. 4 in that the NMOStransistor M₂ is provided between the base of the transistor Q₂ and thesecond power supply node V_(EE), and that an NMOS transistor M₃ isprovided between the emitter of the transistor Q₂ and the second powersupply node V_(EE).

In operation, when the input signal IN is at a high level, NMOStransistors M₂ and M₃ are turned on, and the second power supply nodeV_(EE) and the base and the emitter of the transistor Q₂ are connected,whereby the base and the emitter are brought into the second powersupply potential. The transistor Q₂ is turned off quickly. As a result,output circuit 80 can carry out a switching operation at a high speed.

FIG. 7 is a schematic diagram showing still another embodiment of thepresent invention. An output circuit 90 shown in FIG. 7 is differentfrom output circuit 80 shown in FIG. 6 in that an NMOS transistor M₄connecting between the base and the emitter of the transistor Q₂ inresponse to the input signal IN is provided in place of the NMOStransistors M₂ and M₃. The NMOS transistor M₄ has its source/drainconnected to the base of the transistor Q₂, its drain/source connectedto the emitter of the transistor Q₂, and its gate connected to receivethe input signal IN.

The reason why the NMOS transistor M₄ is connected between the base andthe emitter of the transistor Q₂ is as follows. From the standpoint ofreliability, it is preferred that a bipolar transistor has thebase-emitter junction in a forward direction in its switch offoperation. In the case of the output circuit of FIG. 6, when the currentdrivability of the NMOS transistor M₂ is sufficiently high compared tothe NMOS transistor M₃, there is a possibility that the base-emitterjunction is biased in the reverse direction. However, in output circuit90 shown in FIG. 7, it is possible to completely prevent thebase-emitter junction from being biased in the reverse direction byshorting the base-emitter. Therefore, there is an effect thatreliability of output circuit 90 shown in FIG. 7 is improved.

FIG. 8 is a schematic diagram of a circuit showing still anotherembodiment of the present invention. An output circuit 100 shown in FIG.8 is different from the output circuit shown in FIG. 13 in that theresistance R₁, a PMOS transistor M₅ having a predetermined on-resistancevalue R_(M), a PMOS transistor M₆, an NMOS transistor M₇, and inverter 3are provided in place of differential amplifier 52. Inverter 3 invertsthe input signal IN. The PMOS transistor M₅ is connected to theresistance R₁ in parallel to be turned on/off in response to the inputsignal IN. The PMOS transistor M₆ is connected between the first powersupply node V_(CC) and constant current source 51 to be turned on/off inresponse to the input signal IN. The NMOS transistor M₇ is connectedbetween constant current source 51 and the base of the transistor Q₁ tobe turned on/off in response to the inverted input signal IN. Constantcurrent source 51 provides a steady current similarly to theconventional example.

In operation, when the input signal IN is at a high level, the NMOStransistors M₅ and M₆ are turned on, and the NMOS transistor M₇ isturned off. As a result, a parallel circuit configured of the resistanceR₁ and the on-resistance R_(M) of the PMOS transistor M₅, and the baseof the transistor Q₁ are connected. The combined resistance of theparallel circuit is:

    R.sub.1 ·R.sub.M /(R.sub.1 +R.sub.M)              (7)

The combined resistance is smaller than the resistance R₁. The highlevel of the output signal is:

    V.sub.OH =V.sub.CC -I.sub.b ·R.sub.1 ·R.sub.N /(R.sub.1 +R.sub.M)-V.sub.be                                        (8)

Even if the resistance R₁ is made larger compared to the case of FIG. 1,it is possible to render the high level of the output signalsufficiently high. On the other hand, when the input signal IN is at alow level, the PMOS transistors M₅ and M₆ are turned off, and the NMOStransistor M₇ is turned on, whereby constant current source 51 and thebase of the transistor Q₁ are connected. Therefore, the current I_(b)and the current I₂ from constant current source 51 flow to theresistance R₁, causing the voltage drop at the resistance R₁ to be R₁×(I_(b) +I₂). In the case of the ECL circuit, since the voltage drop isdetermined to be approximately 1 V, it is possible to reduce the currentI₂ by increase of the resistance R₁, whereby power consumption can bereduced.

Output circuit 100 is particularly advantageous when the currentamplification factor hfe of the transistor Q₁ is not high, and the basecurrent I_(b) is large. Since the voltage drop R₁ ×I_(b) at the time ofoutput of a high level is large when the base current I_(b) is large,the high level V_(OH) cannot be rendered sufficiently high unless theresistance R₁ is made small. Therefore, when it is desired to havesufficient voltage drop R₁ ×(I₂ +I_(b)) at the time of output of a lowlevel, the current I₂ must be increased to the extent that theresistance R₁ is decreased. As a result, although power consumptiontends to be increased, the load of the on-resistance R_(M) of the PMOStransistor M₅ prevents power consumption from increasing in outputcircuit 100 shown in FIG. 8.

FIG. 9 is a schematic diagram of a circuit showing still anotherembodiment of the present invention. An output circuit 110 shown in FIG.9 is different from output circuit 100 shown in FIG. 8 in that constantcurrent source 1 having a switching function shown in FIG. 6 is providedin place of a circuit similar to the differential amplifier shown inFIG. 8. The current I₂ generated by constant current source 1 can bemade smaller than the output current I₁ of the constant current sourceof FIG. 1 because of parallel connection between the PMOS transistor M₅and the resistance R₁.

In operation, when the input signal IN is at a high level, NMOStransistors M₂ and M₃ and the PMOS transistor M₅ are turned on, whilethe NMOS transistor M₁ is turned off. As a result, the transistor Q₂ isbrought into the off state quickly, constant current source 1 does notgenerate the current I₂, and the parallel circuit of the PMOS transistorM₅ and the resistance R₁ is connected to the base of the transistor Q₁.An equivalent circuit in this case is the same as the equivalent circuitshown in FIG. 2 having the resistance R₁ connected with theon-resistance R_(M) in parallel. Therefore, even if the resistance R₁ ismade large similarly to the output circuit of FIG. 8, it is possible torender the high level V_(OH) sufficiently high, without the current I₂being generated. As a result, it is possible to reduce power consumptionat the time of output of the high level V_(OH).

On the other hand, when the input signal IN is at a low level, NMOStransistors M₂ and M₃ and the PMOS transistor M₅ are turned off, whilethe NMOS transistor M₁ is turned on. Similar to the output circuit ofFIG. 8, it is possible to increase the resistance value at the time ofoutput of the low level V_(OL) higher than that at the time of output ofa high level. As a result, it is possible to make the voltage drop atthe time of output of a low level larger, thereby decreasing the outputlow level sufficiently. Therefore, according to the embodiment, it ispossible to render the high level sufficiently high and to render thelow level sufficiently low similar to the output circuit of FIG. 8without increasing the current I₂ for bringing the output signal into alow level. In addition to this, it is possible to reduce powerconsumption at the time of output of a high level more substantiallythan the output circuit of FIG. 8.

FIG. 10 is a schematic diagram of a circuit showing still anotherembodiment of the present invention. An output circuit 120 shown in FIG.10 is different from output circuit 110 shown in FIG. 9 in that an NMOStransistor MQ₂ is provided in place of the bipolar transistor Q₂, theresistance R₂ and the NMOS transistor M₃. The other circuitconfiguration is the same as that of FIG. 9.

The NMOS transistor MQ₂ generates a constant current in response to thecontrol voltage V_(CS) of a current potential from control signalgenerating circuit 2 similarly to the bipolar transistor Q₂. The NMOStransistor MQ₂ can be used in place of the bipolar transistor since itis not necessary to generate a current constant unlike the differentialamplifier. The MOS transistor has the merit of being easily made highlyintegrated compared to the bipolar transistor.

FIG. 11 is a schematic diagram of a circuit showing still anotherembodiment of the present invention. The output circuit 130 shown inFIG. 11 is different from output circuit 120 of FIG. 10 in that the NMOStransistor M₂ is removed, that the NMOS transistor M₁ is providedbetween the node N1 and the NMOS transistor MQ₂, and that the NMOStransistor MQ₂ is controlled by the control voltage V_(CS) directly.NMOS transistor M₁ can be provided between the node N1 and the NMOStransistor MQ₂ for the following reason. In the case of the bipolartransistor, there is a problem of reliability when being reverselybiased as described above, although the reverse bias is not especiallyproblematic in the case of the MOS transistor. By turning off the NMOStransistor M₁, even if the drain voltage of the NMOS transistor MQ₂ islower than the gate voltage, it does not affect the reliability.

As described above, according to the present invention, the currentgenerating means generates a current for bringing the output signal intoa low level only at the time of output of a low level, it is possible toreduce power consumption as compared to the conventional example.

By providing switching means having a predetermined on-resistance valuein parallel with resistance means to be turned on/off in response to theinput signal, it is possible to render the high level sufficiently highand the low level sufficiently low without increasing the current. As aresult, it is possible to reduce power consumption at the time of outputof a low level.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

What is claimed is:
 1. An output circuit, comprising:a first powersupply node having a first power supply voltage supplied thereto; asecond power supply node having a second power supply voltage suppliedthereto; a transistor having its collector electrode connected to saidfirst power supply node, and its emitter electrode providing an outputsignal of predetermined logic levels; resistance means having one endconnected to said first power supply node, and the other end connectedto a base electrode of said transistor; and current generating means,connected to the base electrode of said transistor and said second powersupply node, for generating a current in response to an input signal,wherein said current generating means includesi) a current sourceconnected between said second power supply node and the base electrodeof said transistor, ii) control signal generating means for generating acontrol signal to make said current source generate the current, andiii) signal supplying means having switching means connected betweensaid control signal generating means and said current source forsupplying said current source with said generated control signal inresponse to the input signal applied to said switching means.
 2. Theoutput circuit as recited in claim 1, whereinsaid current sourceincludesa first transistor having its collector electrode connected tothe base electrode of said transistor, and its base electrode connectedto receive the control signal from said signal supplying means, andfirst resistance means having one end connected to the emitter electrodeof said first transistor, and another end connected to said second powersupply node.
 3. The output circuit as recited in claim 1, whereinsaidcurrent source further includes switching means connected between thebase electrode and the emitter electrode of said first transistor forbeing turned on/off in a complementary manner to said first transistorin response to the input signal.
 4. The output circuit as recited inclaim 2, whereinsaid current source includesfirst switching meansconnected between the base electrode of said first transistor and saidsecond power supply node for being turned on/off in a complementarymanner to said first transistor in response to the input signal, andsecond switching means connected between the emitter electrode of saidfirst transistor and said second power supply node for being turnedon/off as well as said first switching means in response to the inputsignal.
 5. An output circuit, comprising:a first power supply nodehaving a first power supply voltage supplied thereto; a second powersupply node having a second power supply voltage supplied thereto; atransistor having its collector electrode connected to said first powersupply node, and its emitter electrode providing an output signal ofpredetermined logic levels; resistance means having one end connected tosaid first supply node, and the other end connected to a base electrodeof said transistor; first switching means having a predeterminedresistance value when said first switching means is turned on andconnected to said resistance means in parallel for being turned on/offin response to an input signal; constant current generating meansconnected to said second power supply node for generating a constantcurrent continuously; second switching means connected between saidconstant current generating means and the base of said transistor forbeing turned on/off in a complementary manner to said first switchingmeans in response to the input signal to apply a constant currentgenerated by said constant current generating means to the base of saidtransistor when said second switching means is turned on in response tothe input signal; and third switching means connected between saidconstant current generating means and said first power supply node forbeing turned on/off as well as said first switching means in response tothe input signal.
 6. The output circuit as recited in claim 5,whereinsaid first and third switching means include a MOS transistor ofone conductivity type, and said second switching means includes an MOStransistor of a conductivity type opposite to said one conductivitytype.
 7. An output circuit, comprising:a first power supply node havinga first power supply voltage supplied thereto; a second power supplynode having a second power supply voltage supplied thereto; a transistorhaving its collector electrode connected to said first power supply nodeand its emitter electrode providing an output signal of predeterminedlogic levels; resistance means having one end connected to said firstpower supply node and the other end connected to a base electrode ofsaid transistor; switching means having a predetermined resistance valuewhen said switching means is turned on and connected in parallel to saidresistance means for being turned on/off in response to an input signal;and current generating means connected between the base of saidtransistor and said second power supply node for being turned on/off ina complementary manner to said switching means in response to the inputsignal to generate a current for bringing said output signal into a lowlogic level at said emitter electrode only when said current generatingmeans is turned on in response to the input signal.
 8. The outputcircuit as recited in claim 7, whereinsaid current generating meansincludes a current source connected between said second power supplynode and the base electrode of said transistor, control signalgenerating means for generating a control signal to make constant acurrent generated by said current source, and signal supplying meansresponsive to the input signal for being turned on/off in acomplementary manner to said switching means to supply said currentsource with said generated control signal in the on state.
 9. The outputcircuit as recited in claim 8, wherein said current source includesafirst transistor having its collector electrode connected to the baseelectrode of said transistor and its base electrode connected to receivea control signal from said signal supplying means, and first resistancemeans having one end connected to the emitter electrode of said firsttransistor and another end connected to said second power supply node.10. The output circuit as recited in claim 8, whereinsaid current sourceincludes an MOS transistor having one electrode connected to the baseelectrode of said transistor, another electrode connected to a secondpower supply node, and its control electrode connected to receive acontrol signal from said signal supplying means.
 11. The output circuitas recited in claim 7, wherein said current generating means includesacurrent source connected between said second power supply node and apredetermined node, control signal generating means for generating acontrol signal to make constant a current generated by said currentsource, and second switching means connected between said predeterminednode and the base electrode of said transistor for being turned on/offin a complementary manner to said switching means in responsive to theinput signal.
 12. The output circuit as recited in claim 11, whereinsaidcurrent source includes an MOS transistor, said MOS transistor havingone electrode connected to said power supply node, another electrodeconnected to said predetermined node, and its control electrodeconnected to receive said control signal.